An EEPROM is typically made up of a memory array structure which includes one or more memory arrays. Each memory array is comprised of a plurality of regularly arranged memory cells. FIG. 1 shows a memory array structure of an existing memory. It includes a plurality of memory array rows (i.e., row0, row1, . . . , rowm). Each memory array row includes two subsidiary memory arrays, a first subsidiary memory array 101 and a second subsidiary memory array 102. A switch is disposed between each first subsidiary memory array 101 and the corresponding second subsidiary memory array 102. Moreover, each subsidiary memory array is comprised of n+1 regularly arranged memory cells b0, b1, . . . bn, each of which is configured to record one bit of data.
However, the memory array structure discussed above has a drawback that, when all the memory cells b0, b1, . . . bn are erased (i.e., the value stored in each memory cell is set to 1), a read current flowing in the memory array structure comes to a maximum value. This leads to a great read power consumption which is unfavorable for low power consumption applications and may affect the speed of the memory device.